1. Field of the Invention
The invention relates in general to the fabrication of semiconductor integrated circuits (ICs), and more particularly to the fabrication of deeper vias and smaller interconnects.
2. Description of the Related Art
When the integration of integrated circuits (IC) increases, the number of interconnections increases. Two or more metal layers are designed for fabricating semiconductor integrated circuits. When the integration continues to increase, it is difficult to make an interconnection with a good yield and a good reliability. Damascene is a method of forming an interconnection. The method first forms a trench for interconnection by etching a dielectric layer. Then the trench is filled with metal to form the interconnection. The method satisfies the need to form high reliability and high yield products. Thus, damascene is the best choice in forming an interconnection in sub-quarter micron processes.
Conventional damascene technology has some problems. One of these is the need for two photolithography steps, making the process more complicated and expensive. The other problem is the difficulty of aligning two masks.
FIGS. 1A-1C are cross-sectional views showing a conventional method of fabricating a dual damascene structure. Referring to FIG. 1A, an oxide layer 12 is formed on a substrate 11 in which a region 10 coupling with a wire is formed. The material of the region 10 coupling with a wire is, for example, metal or silicide. A photolithography step of via etching is performed to form a via 13 coupling with the region 10. In FIG. 1B, a photolithography step of reverse metal etching is performed to form trenches 14 and 15 for interconnection. After the etching is finished, a metal 16 is deposited to fill the via 13, the trenches 14 and 15. The metal 16 overflowing the via 13, trenches 14 and 15 is removed by chemical mechanical polishing (CMP) to form the structure showed in FIG. 1C.
FIGS. 2A-2B are cross-sectional views showing another conventional method of fabricating a dual damascene structure. In this method of fabricating dual damascene structures, a silicon nitride layer is formed as an etching stop layer between oxide layers to decrease the disadvantage of over-etching without the etching stop layer.
Referring to FIG. 2A, a first oxide layer 23 is formed on a substrate 22 in which a region 21 coupling with a wire is formed. A silicon nitride layer 25 with an opening 24 is formed on the first oxide layer 23.
Referring to FIG. 2B, a second oxide layer 26 is formed on the silicon nitride layer 25. Then a photolithography step is performed to form a trench. Since the silicon nitride layer 25 is between the first oxide layer 23 and the second oxide layer 26, trenches 27 and 28 are formed and the etching step stops. Because the silicon nitride layer 25 has the opening 24, the etching step continues to form a via 29. Metal is deposited to fill into the trenches 27 and 28 and the via 29. Metal overflowing the trenches 27 and 28 and the via 29 is removed by CMP. Then, the back-end process is performed.
Although the method described above can control the depth of a trench, the method still has some problems. One of the problems is that the silicon nitride layer as an etching stop layer has a high dielectric constant k. The high dielectric constant k increases the parasitic capacitance between interconnections. Furthermore, an etchant used in the photolithography step must have high selectivity of silicon nitride/silicon dioxide. Another of the problems is that the process window is narrow. The etching area shifts when the mask misaligns during etching.
To illustrate this problem, FIG. 3 shows a first oxide layer 32, a silicon nitride layer 33 with a opening and a second oxide layer 34 formed in sequence on a substrate 31 in which a region 30 coupling with a wire is formed. A photolithography step is proceeded by using a mask that shifts towards the right. The shifting of the etching area forms a trench 35 with the same size and a small via 36. When a metal is formed into the trench 35 and the via 36, the contact area that the metal couples with the region 30 is decreased. The decreasing of the contact area makes the contact resistance of interconnections increase. The process has a narrow window and is performed with difficulty.